This year's SELSE workshop features three keynote talks. Bill Dally (Nvidia / Stanford University) will discuss resilience issues for ExaScale systems and some open challenges. Karl Greb (Texas Instruments) will bridge the gap between two domains by helping semiconductor developers understand how silicon errors are considered in current functional safety state-of-the-art. Finally, Tom Pawlowski (Micron) will explore error sources found in the latest generation DRAM and NAND device subsystems and discuss general principles of useful error mitigation methods. A panel discussion with industry experts Norbert Seifert (Intel), Charles Slayman (Cisco), and Vikas Chandra (ARM) will discuss whether all reliability issues have been resolved for late CMOS technologies.
04月01日
2014
04月02日
2014
摘要截稿日期
注册截止日期
2022年05月19日
2022 18th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)2021年04月21日 美国 Los Angeles
2021 17th IEEE Workshop on Silicon Errors in Logic - System Effects2019年03月26日 美国 Palo Alto
2019 15th IEEE Workshop on Silicon Errors in Logic - System Effects2018年04月03日 美国
2018 14th IEEE Workshop on Silicon Errors in Logic - System Effects2017年03月21日 美国 Boston,USA
2017 13th IEEE Workshop on Silicon Errors in Logic - System Effects2016年03月29日 美国 Austin
12th IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE)2015年03月31日 美国
The 11th Workshop on Silicon Errors in Logic - System Effects2013年03月26日 美国
2013 IEEE Workshop on Silicon Errors in Logic - System Effects
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