The 18th HLDVT workshop aims to bring together a community of researchers in the areas of design validation, and test of hardware, software, cyber-physical systems, biological systems, and biochips. The workshop addresses the integration of multiple functions on-chip/in-system at higher levels of design abstraction, and the techniques and methodologies for modeling, analyzing, and validating such systems. In particular, the workshop has become a unique forum for researchers and practitioners to discuss the practical issues associated with validation of extremely large designs.
Topics of interest include, but are not limited to:
Simulation-Based Validation
Formal Verification, and Hybrid Methods
Design Abstraction, and Behavioral Modeling
Error Trace Interpretation, and Debugging
Functional safety/safety-critical system verification
On-Chip, and Core-Based Testing
Test Generation for Defects, Design Errors, and Delay Faults
Hardware/Software, and Mixed-signal System Co-Validation
Emulation, and Prototyping
Post-silicon Validation, and Debug.
Paper Submission: The Program Committee invites authors to submit papers not to exceed 8 pages in the IEEE two-column conference format with 10-pt font size, describing original and unpublished work. It will be possible to purchase up to 2 additional pages at $100 per page, for a total of 10 pages per paper. Panels and special session proposals are also invited. All submissions must be made electronically in PDF format.
10月07日
2017
10月08日
2017
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2016年10月07日 美国 Santa Cruz, CA, USA
2016 IEEE International High Level Design Validation and Test Workshop
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