2017年 RTL和高级测试研讨会 Workshop on RTL and High Level Testing 2017

活动简介

The goal of this workshop is to bring researchers and practitioners of VLSI testing from all over the world together to exchange ideas and experiences in register transfer level (RTL) and high level testing. WRTLT'17, the 18th workshop, will be held in conjunction with the 26th Asian Test Symposium (ATS'17) in Taipei, Taiwan. We hope and expect this workshop provides an ideal forum for deep discussion on this important topic for the future system-on-a-chip (SoC) designs and 3D integrated circuits.

征稿信息

征稿范围

Areas of interest include but are not limited to:

RTL fault modeling, RTL ATPG, RTL DFT, RTL BIST
High-level/behavior fault modeling, testing and synthesis for testability
Functional fault modeling and test bench generation
3D IC testing
SoC/NoC testing, test scheduling, core-based testing, interconnect testing
Dependable SoC: design for dependability, self-repair techniques, fault-tolerant SoCs
Microprocessor testing and design verification
Low power testing and Test compression
Hardware trojan detection and secure testing