CAV 2017 is the 29th in a series dedicated to the advancement of the theory and practice of computer-aided formal analysis and synthesis methods for hardware and software systems. CAV considers it vital to continue spurring advances in hardware and software verification while expanding to domains such as cyber-physical, social, and biological systems. The conference covers the spectrum from theoretical results to concrete applications, with an emphasis on practical verification tools and the algorithms and techniques that are needed for their implementation. The proceedings of the conference will be published in the Springer LNCS series. A selection of papers will be invited to a special issue of Formal Methods in System Design and the Journal of the ACM.
Topics of interest include but are not limited to:
Algorithms and tools for verifying models and implementations
Algorithms and tools for system synthesis
Mathematical and logical foundations of verification and synthesis
Specifications and correctness criteria for programs and systems
Deductive verification using proof assistants
Hardware verification techniques
Program analysis and software verification
Software synthesis
Hybrid systems and embedded systems verification
Compositional and abstraction-based techniques for verification
Probabilistic and statistical approaches to verification
Verification methods for parallel and concurrent systems
Testing and run-time analysis based on verification technology
Decision procedures and solvers for verification and synthesis
Applications and case studies in verification and synthesis
Verification in industrial practice
New application areas for algorithmic verification and synthesis
Formal models and methods for security
Formal models and methods for biological systems
07月22日
2017
07月28日
2017
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