The workshop's areas of interest include (but are not limited to) the following topics:

• Defects due to Wafer Thinning

• Defects in Intra-Stack Interconnects

• DfT Architectures for 3D-SICs

• EDA Design-to-Test Flow for 3D-SICs

• Failure Analysis for 3D-SICs

• Fault-Tolerant Design for 3D-SICs

• Handling and Testing Singulated Stacks

• Interposer Testing

• Known-Good Die / Stack Testing

• Power and Heat Dissipation during Test

• Pre-Bond, Mid-Bond and Post-Bond Testing

• Reliability of 3D-SICs

• Stacking Yield of Dies and Interconnects

• Standardization for 3D Testing

• Supply Chain and Logistic Issues

• System/Board Test Issues for 3D-SICs

• Test Cost Modeling for 3D-SICs

• Test Flow Optimization for 3D-SICs

• Tester Architecture incl. ATE and BIST

• Thermal/Mechanical Stress in 3D-SICs

• TSV Test, Redundancy, and Repair

• Wafer Probing and Probe Marks of 3D-SICs