第九届国际网络芯片架构研讨会 9th International Workshop on Network on Chip Architectures

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活动简介

Current multicore architectures formed by tens of processing cores will be soon replaced by the next generation of manycore architectures with hundreds of cores. In fact, the International Technology Roadmap for Semiconductors foresees that the number of Processing Elements (PEs) that will be integrated into a System-on-Chip (SoC) will be in the order of thousand within the 2020. As the number of communicating elements increases, there is a need for an efficient, scalable and reliable communication infrastructure. As technology geometries shrink to the deep submicron regime, however, the communication delay and power consumption of global interconnections become the major bottleneck. The Network-on-Chip (NoC) design paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication issues such as performance limitations of long interconnects, and integration of large number of PEs on a chip.

The goal of NoCArc workshop is to provide a forum for researchers to present and discuss innovative ideas and solutions related to design and implementation of multi-core systems on chip. The workshop will focus on issues related to design, analysis and testing of on-chip networks.

征稿信息

重要日期

2016-08-08

初稿截稿日期

2016-09-01

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2016-09-08

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征稿范围

The workshop will focus on issues related to design, analysis and testing of on-chip networks. The topics of specific interest for the workshop include, but are not limited to:

NoC Architecture and Implementation

Topologies, routing, flow control
Managing QoS
Timing, synchronous/asynchronous communication
Reliability issues
Design methodologies and tools
Signaling & circuit design for NoC links
NoC Analysis and Verification

Power, energy and thermal issues

Benchmarking and experience with NoC-based systems
Modeling, simulation, and synthesis
Verification, debug and test
Metrics and benchmarks
NoC Application

Mapping of applications onto NoCs

NoC case studies, application-specific NoC design
NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
NoC designs for heterogeneous systems
On-Chip Communication Optimization

Communication efficient algorithms

Multi/many-core communication workload characterization and evaluation
Energy efficient NoCs and energy minimization
NoC at System-level

Design of memory subsystem

NoC support for memory and cache access
OS support for NoCs
Programming models including shared memory, message passing and novel programming models
Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks
Emerging NoC Technologies