摘要清单
我的稿件
440
Hardware Implementation of Connected Components Analysis for the vision-based tactile perception image终稿

lutong zhao, chun zhang*, mingchao yin, chuanbo hu, yuanhang zhang, wen jia

全体主题 > Digital Circuits

427
A Low Power Verification Oriented Reusable Functional Verification Platform Based on UVM全文被拒

SUN Jian*

全体主题 > Digital Circuits

399
Design Method of LEO Satellite Communication ASIC终稿

Changhong Wang*, Fei Gao

全体主题 > Digital Circuits

394
A Novel Hardware/software Co-design for An Efficient RSA System终稿

Yuyang Pan, Liji Wu*, Xiangmin Zhang

全体主题 > Digital Circuits

379
The Multi-input MRL Logic Gate and Its Application终稿

Xiaole Cui*, Li Qu, Xiaoxin Cui, Ye Ma

全体主题 > Digital Circuits

357
A method to transform synchronous pipeline circuits to bundled-data asynchronous circuits using commercial EDA tools终稿

Hui Wu, Weijia Chen, Zhe Su, Shaojun Wei, Anping He, Zhihua Wang, Hong Chen*

全体主题 > Digital Circuits

355
Energy and Area Efficient 11-T Ternary Content Addressable Memory for High-Speed Search终稿

Neelam Surana*, Diptesh Datta, Piyush Dewangan, Joycee Mekie

全体主题 > Digital Circuits

347
A New Multilevel Interpolated TDC Method Based on a Two-Step Synchronizer终稿

Dahe Liu, Xueyou Shi, Guangyi Chen, Wengao Lu*, Zhongjian Chen

全体主题 > Digital Circuits

重要日期

  • 会议日期

    06月12日

    2019

    至

    06月14日

    2019

  • 06月12日 2019

    初稿截稿日期

  • 06月14日 2019

    注册截止日期

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Xi'an University of Technology
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