651 / 2019-04-02 18:43:21
Enhanced LVTSCR with High Holding Voltage in Advanced CMOS technology
Electrostatic discharge (ESD),LVTSCR,holding voltage,latch-up immunity
终稿
Meichen Huang / University of Electronic Science and Technology of China
Feibo Du / University of Electronic Science and Technology of China
Fei Hou / University of Electronic Science and Technology of China
Wenqiang Song / University of Electronic Science and Technology of China
Jizhi Liu / University of Electronic Science and Technology of China
Zhiwei Liu / University of Electronic Science and Technology of China
In this paper, an improved low voltage triggered silicon-controlled rectifier (LVTSCR) for electrostatic discharge protection is proposed. By carefully optimizing the electric field distribution at the junction of P-WELL and N-WELL in LVTSCR,the holding voltage of the enhanced LVTSCR (ELVTSCR) can be effectively increased to improve latch-up immunity. TCAD simulation indicates that compared with traditional LVTSCR, the proposed ELVTSCR has higher and adjustable holding voltage as well as comparable trigger voltage, making it suitable to provide ESD solutions for high voltage (HV) applications in advanced CMOS technology.
重要日期
  • 会议日期

    06月12日

    2019

    06月14日

    2019

  • 06月12日 2019

    初稿截稿日期

  • 06月14日 2019

    注册截止日期

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