618 / 2019-03-15 22:51:53

A 12-bit 200MS/s Pipelined-SAR ADC in 65-nm CMOS with 61.9 dB SNDR

Pipelined-SAR ADC；MDAC；hybrid architecture

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Abstract—This paper presents a 12-bit 200MS/s Pipelined-SAR hybrid architecture ADC with a 3.5-bit MDAC for the first stage and a 9-bit SAR ADC for the second stage. In the MDAC, a low-power high DC-gain class-AB residue amplifier is proposed to achieve 80dB DC-gain and 0.8GHz unity-gain-bandwidth (UGB). In the SAR ADC, two techniques are applied to accelerate the comparison speed to meet the requirement of high-speed ADC. Fabricated in a 65nm CMOS process, the ADC occupies an area of 0.21 mm2 and consumes a power of 7.3 mW. The measured Nyquist SFDR and SNDR are 71.2 dB and 61.9 dB at 200 MS/s. The ADC achieves a FoM of 35.6 fJ/conversion-step.