536 / 2019-03-11 15:09:42
Power Estimation of Embedded SRAMs using BIST Algorithms
power estimation,SRAM,built-in self-test
全文录用
Yang Zhao / Chinese Academy of Sciences, Institute of Microelectronics
Lan Chen / Institute of Microelectronics, Chinese Academy of Sciences
As more and more memories are used on a chip for graphic rendering and cloud computing purpose, power estimation of memories in a chip on an automatic test equipment (ATE) without the aid of functional patterns is a rarely new practice. Power dissipated by embedded SRAMs under normal operation is critical to power estimation. This paper describes a method that utilizes memory BIST architecture and algorithms to mimic the normal functional operation of embedded SRAMs with various lengths, in order to estimate power consumption as early as wafer level in an ATE environment.
重要日期
  • 会议日期

    06月12日

    2019

    06月14日

    2019

  • 06月12日 2019

    初稿截稿日期

  • 06月14日 2019

    注册截止日期

承办单位
Xi'an University of Technology
联系方式
历届会议
移动端
在手机上打开
小程序
打开微信小程序
客服
扫码或点此咨询