445 / 2019-02-27 13:28:23
Design of Ultra-Wideband Sampling Circuit Based on Multi-Channel Synchronous
Ultra-wideband, Multi-channel Synchronous; High-speed ADC, 4GHz bandwidth, domestic chip
终稿
xu rui-rong / The 723 Institute of CSIC
li chun-lai / The 723 Institute of CSIC
hu jin-xian / The 723 Institute of CSIC
li ren-gang / The 723 Institute of CSIC
song shi-qian / The 723 Institute of CSIC
wang ning / The 723 Institute of CSIC
The performance of sampling chip is critical to the performance of the digital receiving system. The paper proposes an implementation solution of high-performance multi-channel synchronous sampling circuit with 4GHz instantaneous bandwidth and 10.24Gsps sampling rate which is based on the domestic high-speed ADC chip. The paper mainly describes the design of high-speed ADC chip, which includes register control, power supply design, clock design, and interface design. Lastly, the design and debugging of software and hardware are carried out as per the functional requirements of the boards. According to the result of experimental test, the FPGA is able to receive the multi-channel ultra-wideband high-frequency signal generated by the signal generator perfectly, which means that the synchronous sampling design based on high-speed ADC chip is able to satisfy the design requirements and accomplishes the purpose of 10.24Gsps sampling and 4GHz bandwidth synchronous signal reception.
重要日期
  • 会议日期

    06月12日

    2019

    06月14日

    2019

  • 06月12日 2019

    初稿截稿日期

  • 06月14日 2019

    注册截止日期

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