432 / 2019-02-27 07:11:02

Continuous-Time Sigma-Delta Modulator Using 4-Bit SAR Quantizer

sigma-delta, continuous-time, SAR quantizer

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In this paper, a third-order single-loop continuous-time sigma-delta modulator with a 4-bit asynchronous SAR quantizer is presented. The RC integrator is adopted to obtain high linearity. By using a 4-bit SAR quantizer, the power consumption and area of the design can be lowered. Besides, an excess loop delay compensation circuit is designed for the conversion of SAR ADC. To improve the accuracy, the first feedback DAC adopts the current-steering topology corrected by the data weighted averaging (DWA) algorithm. According to the simulation results, when the mismatch of DAC below 0.3%, the modulator achieves 74 dB SNDR with 1.28 MHz bandwidth, and the ENOB exceeds 12 bits.