380 / 2019-01-23 21:55:40

Under voltage lockout circuit design for enhanced GaN HEMT drive

Enhanced GaN HEMT ; Parasitic PNP; Threshold hysteresis ; Under voltage lockout

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In order to monitor the stability of the power supply of the Enhanced GaN HEMT half-bridge driver chip, an under voltage lockout circuit suitable for driving the chip that was designed. First, a Spice model of the enhanced GaN HEMT device was used to build the circuit, which analyzes the basic electrical characteristics of the device and simulates the effects of parasitic inductances of the enhanced GaN HEMT device on the circuit due to PCB traces and land patterns, the layout of the optimized half-bridge switch node waveform was tested. Then, using the I-V characteristics of CSMC 0.5um CMOS process of parasitic PNP transistor, An under voltage lockout circuit with a Schmitt trigger and an inverter at the output was designed and the circuit's drive capability was improved. The layout of the circuit module was drawn using the Virtuoso Layout Editor in Cadence software. When the power supply voltage rises/falls between 3-5V, the rising/falling threshold is 4.1V/3.7V, and the threshold hysteresis is 400mV. When the temperature changes from -40°C to 125°C, there is a small temperature drift. This under voltage lock out circuit can effectively prevent the power supply from abnormal transition due to noise and load-induced interference and the incomplete conduction state of the enhanced GaN HEMT.