377 / 2019-01-23 10:58:20

Linearity optimization of current steering DAC based on improved layout topology

Digital-to-Analog Converter; Segmented current steering; Random layout; Nonlinearity

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The influence of current mismatch on linearity of current steering DAC is theoretically discussed. Q2 random walk scheme that can reduce the secondary error of current mismatch is utilized for optimizing the linearity of DAC. A 10 bit DAC is realized in 0.18 µm CMOS. Measurement results show that the differential non-linearity (DNL) and the integral non-linearity (INL) of the DAC are 0.71 LSB and 1.02 LSB. With 500 MS/s sampling rate and 1.465 MHz input frequency, the spurious free dynamic range (SFDR) and the effective number of bits (ENOB) are 65.6 dB and 9.2 bit, respectively.