活动简介

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, chip-scale, and multichip package-scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, packaging, embedded systems, co-design, and design automation.

征稿信息

重要日期

2017-05-08
摘要截稿日期
2016-05-15
初稿截稿日期
2017-07-01
初稿录用日期
2017-08-01
终稿截稿日期

征稿范围

The International Symposium on Networks-on-Chip (NOCS) is the premier event dedicated to interdisciplinary research on on-chip, chip-scale, and multichip package scale communication technology, architecture, design methods, applications and systems. NOCS brings together scientists and engineers working on NoC innovations and applications from inter-related research communities, including computer architecture, networking, circuits and systems, packaging, embedded systems, and design automation. Topics of interest include, but are not limited to:

NoC Architecture and Implementation

  • Network architecture (topology, routing, arbitration)
  • NoC Quality of Service
  • Timing, synchronous/asynchronous communication
  • NoC reliability issues
  • Network interface issues
  • NoC design methodologies and tools
  • Signaling and circuit design for NoC links
     

NoC Application

  • Mapping of applications onto NoCs
  • NoC case studies, application-specific NoC design
  • NoCs for FPGAs, structured ASICs, CMPs and MPSoCs
  • NoC designs for heterogeneous systems, fused CPU-GPU architectures, FPGA-based systems, etc
  • Scalable modeling of NoCs

Novel NoC Technologies

  • New physical interconnect technologies, e.g., carbon nanotubes, wireless NoCs, through-silicon, etc.
  • NoCs for 3D and 2.5D packages
  • Package-specific NoC design
  • Optical, RF, & emerging technologies for on-chip/in-package interconnects
  • In-memory network and NoCs for new memory technologies
     

NoC at the Un-Core and System-level

  • Design of memory subsystem (un-core) including memory controllers, caches, cache coherence protocols in NoCs
  • NoC support for memory and cache access
  • OS support for NoCs
  • Programming models including shared memory, message passing, and novel programming models
  • Issues related to large-scale systems (datacenters, supercomputers) with NoC-based systems as building blocks

NoC Analysis and Verification

  • Power, energy and thermal issues (at the NoC, un-core and/or system-level)
  • Benchmarking & experience with NoC-based hardware
  • Modeling, simulation, and synthesis of NoCs
  • Verification, debug, and test of NoCs
  • Metrics and benchmarks for NoCs
     

On-Chip Communication Optimization

  • Communication efficient algorithms
  • Communication workload characterization and evaluation
  • Energy efficient NoCs and energy minimization
     

Off-Chip and Rack-Level Communication

  • All aspects of inter-chip network design
  • All aspects of rack-level network design
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重要日期
  • 会议日期

    10月19日

    2017

    10月20日

    2017

  • 05月15日 2016

    初稿截稿日期

  • 05月08日 2017

    摘要截稿日期

  • 07月01日 2017

    初稿录用通知日期

  • 08月01日 2017

    终稿截稿日期

  • 10月20日 2017

    注册截止日期

主办单位
IEEE Circuits and Systems Society
IEEE Council on Electronic Design Automation
Association for Computing Machinery
协办单位
IEEE Circuits and Systems Society
IEEE Council on Electronic Design Automation
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