34 / 2015-09-24 17:36:07

A 14 bit 2.5 GS/s DAC based on Multi-Clock Synchronization

7881,7880,7879

This paper presents a 14-bit 2.5GS/s current-steering segmented DAC with a new technology of synchronization, called Multi-clock synchronization, which is used to optimize the timing between the internal digital and analog domains. The quad-switch architecture is also adopted to mask the code-dependent glitches. The full-scale output current can be programmed over the 10mA to 30mA range, and the typical full-scale output current is 20mA. The device is manufactured on a standard 0.18μm CMOS process and operates from 1.8V and 3.3V supplies.