We describe the performance of a passive integrator which consists of a resistor and a capacitor in series. A circuit model of the passive integrator taking into account the parasitic parameters of each element is proposed. The circuit simulation results show that the upper-limited response frequency of the passive integrator is mainly decided by the parasitic capacitance of the integrator’s resistor and the parasitic inductance of its capacitor. The parasitic capacitance of the resistor should be degraded at the expense of its parasitic inductance since this parameter does not deteriorate its upper-limited response frequency remarkably. The capacitor of circular configuration is preferred as it is helpful to decrease its parasitic inductance. We have also designed a passive integrator with a 2 kΩ metallic glaze resistor and 1 nF annular capacitor. The actual bandwidth of this passive integrator is measured by a vector network analyzer, and the upper-limited response frequency of the passive integrator is about 1.2 GHz which is better than the commercial product.
 

passive integrator,circuit simulation,bandwidth