Deterioration Mechanisms of High Voltage Press-Pack IGBT under Power Cycling Test
Yaxin Zhang1, Lingyu Zhu1, Cao Zhan1, Libo Dou2, Weicheng Wang1
1Xi’an Jiaotong University, Xi’an, China
2University Of Nebraska-Lincoln, Lincoln , US
17772622706@163.com
Purpose/Aim
High voltage press-pack insulated gate bipolar transistors (PPIs) are widely utilized in MMC-HVDC due to its merits like, short-circuit failure mode, double side cooling etc. To ensure the long-term reliability of PPIs in field operation, the in-depth understanding of the deterioration mechanism is essential. Thus, the power cycling test, which is the commonly used approach to investigate the deterioration mechanism of PPIs, is conducted.
Experimental/Modeling methods
In this paper, by keeping the on-time of the load current at 5s, the power cycling test is implemented on two samples. The evaluation curves of both the heating saturation voltage, equivalent thermal resistance and gate threshold voltage are recorded during the tests.
Results/discussion
One sample failed after 70K cycles shows that the saturation voltage increases by above 10%, while the thermal resistance remains unchanged. Nevertheless, both the saturation voltage and thermal resistance of another sample remain unchanged after 400K cycles. After power cycling test, the surface morphology of the additional metallization areas are observed by the micro-optical methods.
Conclusions
The experimental results show that the deterioration mechanism of PPI under power cycling test in long-term scale is different from that in short-term duration. Fretting wear occurs at the edge of the additional metallization area among all samples, while cracks appear in the emitter surface of the samples suffering long-term test.