332 / 2022-03-15 15:16:27

Research about electrostatic discharge on system-in-package chip substrate

Electrostatic discharge (ESD),SiP,Interconnect

IEEE ICHVE 2022 / 1-PAGE ABSTRACT

Research about electrostatic discharge on system-in-package chip substrate

Yu-Hui Lv, Hai-Bao Mu and Yi-Tong Yao

State Key Lab of Electrical Insulation and Power Equipment, School of Electrical Engineering, Xi'an Jiaotong University, Xi’an, Shaanxi, 710049, China

790269276@qq.com

Purpose/Aim

Intelligent chip based on the technology of SiP (System in Package) is the key technology for digital monitoring of power transformers. However, in complex electromagnetic field environments, the static electricity accumulation on the substrate of SiP chip will cause electrostatic discharge (ESD), leading to failure. In order to improve the reliability of SiP chips, it is necessary to research the phenomena and reasons of static electricity accumulation and find ways to reduce ESD.

Experimental/Modeling methods

Three typical interconnect models (parallel interconnects, corner interconnects, interconnect with pad) used in SiP-chip LTCC (Low Temperature Co-Fired Ceramic) substrate were constructed to analysis the static electricity accumulation on substrate. Different amplitudes and frequencies of ground potential counterattacks were simulated to research the effect of various pulse voltages to the static electricity accumulation and ESD.

Results/discussion

The corner interconnects are more likely to induce ESD compared with other two kinds of models. Static electricity accumulation possibly causes the strongest electric field, high voltage, large instantaneous current and a magnetic field pulse. Besides, the more concentrated parts of chip components, the higher likelihood of ESD.

Conclusions

The ESD current mainly propagates through the substrate wiring and device edges, presumably resulting in the discharge between the SiP chips, pins, and sharp edges of component, etc. It was found that the edge of substrate is the place where static electricity accumulation most likely to happen, so it is considerable to have a larger space near the edge of substrate.