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An SRAM Test Quality Improvement Method For Automotive chips
编号：59 访问权限：仅限参会人 更新：2021-08-24 20:47:32 浏览：418次 口头报告

报告开始：2021年08月20日 20:00（Asia/Shanghai）

报告时间：20min

所在会场：[IS] Industrial Session [IS4] B5. Industry Practice in SoC and Memory Test

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摘要
Automotive chips have high requirements on chip test quality. The degree of defects covered by the SRAM test algorithm directly determines the test quality of SRAM. With the evolution of IC manufacturing technology, the defect modeling of SRAM becomes more and more complicated. How to establish a complete test algorithm has become a challenge in the industry. Currently, the industry develops a new test algorithm by establishing defect models on the advanced process nodes. However, the defect model is different from the defect in the actual process. The mass production test shows that many chips are in the critical defect state and cannot be detected. In this paper, we propose an improved memory defect analysis method, and develop a novel defect and test scheme. The mass production test results show that this test scheme can detect the critical defect chips effectively.
 
关键词
MBIST, test algorithm, dynamic faults, defect simulation,automotive
报告人
Tuanhui Xu
employees

Tuanhui xu is a senior DFT engineer at HiSilicon Semiconductor. He is responsible for researching memory defects and memory fault models, developing test algorithms, and analyzing faulty chips. He received a bachelor's degree in electronic information engineering from Xi'an Electronic University in 2006, and a master's degree in computer science from China Electronic Technology Group in 2010. He joined HiSilicon Semiconductor Corporation in 2011 and engaged in DFT-related work.
 

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重要日期

  • 会议日期

    08月18日

    2021

    至

    08月20日

    2021

  • 05月10日 2021

    初稿截稿日期

  • 08月16日 2021

    提前注册日期

  • 08月19日 2021

    报告提交截止日期

  • 08月20日 2021

    注册截止日期

主办单位
IEEE
Tongji University
Chinese Computer Federation
承办单位
Tongji University
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